1. Field of the Invention
The present invention generally relates to computer systems, and more particularly to a system for bridging a system processor bus with multiple PCI buses, to provide improved performance and fault tolerance.
2. Discussion of the Related Art
In computer system design, a principal objective is to continually design faster and more efficient computer systems. One of the bottlenecks that has limited the performance of personal computers in the past has been the maximum specified speed of the ISA bus. In original IBM PC AT computers manufactured by IBM Corp., the I/O bus operated with a data rate of 8 MHz (BCLK=8 MHz). This was an appropriate data rate at that time since it was approximately equivalent to the highest data rates which the CPUs of that era could operate on the host bus. CPU data rates are many times faster today, however, so the slow speed of the I/O bus severely limits the throughput of systems today. One solution for this problem has been the development of local bus standards, by which certain devices which were traditionally located on the I/O bus can now be located on the host bus--e.g., the VESA VL-Bus Local Bus Standard.
Another solution to the problem has been the development of another standard, referred to herein as the PCI standard. The PCI bus achieves very high performance, in part because its basic data transfer mode is by burst. That is, data is always transferred to or from a PCI device in a known sequence of data units defined by a known sequence of data unit addresses in an address space. In a "cache line" burst mode, a predetermined number of transfers take place. In a "linear" burst mode, any number of transfers (including 1) can take place to/from linearly sequential addresses until either the initiator or the target terminates the transaction. In either mode, the initiator need only specify the starting address because both parties know the sequence of addresses which follow. The implementation of the PCI bus is well known in the industry and its specifications are available to the public.
Many computing systems, including many personal computers, have a single PCI bus that extends to various devices on a motherboard, as well as to several expansion slots on the motherboard. Expansion cards may be inserted into the expansion slots to provide expanded capabilities for the computers. In the context of the PCI bus, multiple PCI devices may share a single PCI bus and, in this regard, multiple PCI devices may be provided on separate expansion cards. More advanced systems may, however, provide multiple PCI buses.
By way of illustration, reference is made to FIG. 1, which is a block diagram illustrating a multiple PCI bus configuration, as is known in the prior art. The figure illustrates a computing system having a memory 10, a CPU 12, and other devices (not shown) interconnected for communication along a system bus 14. At least one PCI bus 16, 18 is also provided as part of the computing system. A device known as a bridge 20 is provided as a buffer/translator between the PCI bus 16 and the system bus 14. More specifically, and as is known, the signaling and protocol on a PCI bus is different than that on a system bus 14. A bridge is a device that "bridges" the communications between a system bus 14 and a PCI bus 16. As previously mentioned, multiple PCI devices may be configured for communication along a single PCI bus. In this regard, FIG. 1 illustrates four slots 22, 24, 26, and 28 that are disposed for communication with the PCI bus 16. These slots may be expansion slots for receiving plug in cards that may communicate across the PCI bus 16.
As is further known, isolation circuitry 32, 34, 36, and 38 may be provided in higher-end systems to allow on-line replacement of PCI device cards. In this regard, the isolation circuitry 32 electrically isolates PCI slot 22 from PCI slots 24, 26, and 28, which share the same PCI bus. The isolation circuitry serves to protect PCI devices from an electrical short, signal spike, or other electrical irregularities that often occur coincident with on-line replacement of PCI card devices.
There is, however, a limitation on the number of PCI devices that may be interconnected along a single PCI bus 16. This limitation may differ from system to system, but generally results from electrical loading limitations and/or the recognition that an excessive number of PCI devices sharing a common bus will generally result in an over contention for the bus, thereby reducing system performance and efficiency. Accordingly, systems are known to provide multiple PCI buses. In this regard, a second PCI bus 18 is illustrated in FIG. 1. It is illustrated in dash line to represent the notion that it is an optional bus, which is not necessarily provided in all systems. A similar multiple slot/isolation circuitry configuration may be provided on the second bus as well. Both buses 16 and 18 interface to the system bus 14 by way of a common bridge 20.
Generally, however, no more than two PCI buses are provided in a system having a configuration similar to that of FIG. 1. The reason results simply from physical limitations of devices. Although the specific number may vary from system to system, a PCI bus typically comprises about one hundred conductors, in order to carry all the necessary data, address, and control signals. Therefore, a bridge circuit 20 supporting two PCI buses would require over two hundred signals to interface to external circuitry. These include the approximately two hundred conductors required to interface to the two PCI buses, as well as an additional plurality of pins required to interface to the system bus 14. Accommodating additional PCI buses is, therefore, limited by the physical limitation required in the number of conductors for interfacing to the PCI buses.
One problem with the systems of the type illustrated in FIG. 1 relates to the isolation between various PCI devices. While the isolation circuitry 32, 34, 36, and 38 electrically isolates one PCI device from another, it does not provide "logical" isolation between the various PCI devices. For example, suppose a PCI device residing in slot 22 requests data but, due to a failure on the device, never accepts the data from the PCI bus 16. This could, in many systems, hold up the PCI bus 16 preventing other PCI devices from communicating across the PCI bus, because the PCI bus is stalled waiting for the device in slot 22 to accept data. In this way, a failure of one PCI device may affect the system operation by starving other PCI devices that need to share the common PCI bus 16. In this regard, and as will be appreciated by those skilled in the art, I/O cards are generally characterized by a higher replacement frequency that other types of cards, thereby making on-line replacement (and the need for the isolation circuitry) relatively important, in high-end systems requiring a high level of availability.
Another shortcoming with systems of the type illustrated in FIG. 1 relates to PCI device inconsistencies. More specifically, PCI devices are known to operate in either a 32 bit or 64 bit mode. Also, some PCI devices now operate at 66 MHz while others operate at 33 MHz. In present systems, upon system reset (or power-up) the system will evaluate the various devices along a PCI bus to configure the system for operation therewith. If, for example, three PCI devices in slots 22, 24, and 26 operate at the faster 66 MHz operation, while a fourth PCI device in slot 28 operates at the slower 33 MHz operation, the system will configure all the PCI devices on bus 16 to operate at the slower 33 MHz speed, thereby negating the performance advantage that could otherwise be obtained from the faster PCI cards in slots 22, 24, and 26. As a practical matter, on a four slot bus like that shown in the drawings, it is unlikely that any of the cards could be configured to operate at 66 Mhz, due to electrical loading.
A similar inefficiency occurs when one or more of the PCI cards along a given PCI bus operates in a 32 bit (as opposed to 64 bit) mode. Although the various cards could operate, individually, at their data width capacity, operating 32 bit cards on a 64 bit bus results in wasted bandwidth, and thus less that optimal efficiency.
Accordingly, there is a desire to provided an improved system for interfacing (or bridging) a system bus to multiple bus that overcomes the above-identified and other shortcomings.